In conventional transistor-transistor logic (TTL) and diode-transistor logic (DTL) devices, logical values corresponding to binary "1" and "0" are ordinarily represented at the output by a high level voltage V.sub.oh, for example greater than 2.4 volts, and a low level voltage V.sub.ol, for example less than 0.8 volts. In positive logic, the high level binary "1" is derived from a voltage source V.sub.cc which "sources" the current to the output when a binary "1" is to be delivered by the output gate. When a binary "0" is required at the output, the output gate blocks sourcing current and instead "sinks" the current from the output load to ground so that the low level voltage V.sub.ol appears at the output of the logic gate. Thus, the typical TTL output gate functions by "sourcing" and "sinking" current at the output according to whether a binary "1" (high level voltage) or a binary "0" (low level voltage) is the desired outcome of previously executed logical operations. In negative logic the representation of binary 1 and 0 by high and low level voltage is reversed.
A conventional low power Schottky TTL output device 10 is illustrated in FIG. 1. Several elements or stages can be identified in such a TTL output gate. The "pullup" element 11 for sourcing current from the higher level voltage V.sub.cc and delivering binary 1 consists of transistors Q5 and Q6 forming a Darlington transistor pair that can supply a relatively large current between the high level voltage source V.sub.cc and the output V.sub.o when a much smaller current is applied to the base of Q5. The "pulldown" element or stage 12 for sinking current from the output to ground consists of transistor Q3 with conventional squaring network 16 at its base comprised of resistors R7 and R8 and transistor Q4. The phase splitter element or stage 13 consists of transistor Q1 which receives the data signal input to the gate in the form of a high or low level voltage at V.sub.in and controls the pullup and pulldown elements for either sourcing or sinking current at the output 14 as determined by the data signal input to the gate.
When a low voltage or potential appears at the input 15, a low voltage also appears at the base of phase splitter transistor Q1 and this transistor is deprived of base drive current so that it no longer conducts current through its collector to emitter thereby turning off pulldown transistor Q3. Ideally, the output V.sub.o of the gate is therefore isolated from ground. At the same time, because Q1 is non-conducting, the high level voltage V.sub.cc appears at the base of sourcing transistor Q5 supplying base current for transistor Q5 which turns on and supplies current to the base of Q6 which in turn becomes conducting and "sources" current from V.sub.cc to the output V.sub.o. The TTL logic gate is therefore inherently inverting as a binary 0 at the input V.sub.in represented by a low voltage level generates a binary 1 at the output represented by voltage level V.sub.oh.
When a binary 1 appears at the input, current from R1 supplies base drive to transistor Q1, Q1 becomes conducting, sinking current from the base of Q5 and therefore turning off the Darlington transistor current source represented by transistors Q5 and Q6. Current from high level voltage V.sub.cc is therefore no longer sourced to the output 14. At the same time, pulldown transistor Q3 becomes conducting through its collector to emitter to ground as a result of the current supplied to its base and begins to discharge current from whatever load capacitance may be coupled to the output 14 of the gate, bringing the output V.sub.o to a low level potential corresponding to binary 0.
As shown in FIG. 1 and in later figures, some of the transistor and diode components are typically Schottky diodes and transistors indicated by the opposite square hooks in the schematic symbols. The Schottky clamping effected by an internal modification in these devices produces quicker turn-off during switching. A transistor logic output gate of the type illustrated in FIG. 1 however, suffers the disadvantage of high power consumption and retarded switching during transition from low to high potential at the output as hereafter described.
In FIG. 2 there is illustrated an advanced Schottky TTL output gate 20 according to the present state of the art. The elements of the device include the pullup element 21, pulldown element 22 with squaring network 26 at the base of pulldown transistor Q3, and two gain stage phase splitter 23. This output device is similar to the low power Schottky TTL output gate described above except that an additional stage of gain has been added to the phase splitter element. Thus, components in FIG. 2 performing the same function as described above with reference to FIG. 1 are similarly designated and an additional stage of gain for the phase splitter element has been added by way of transistor Q2. A high level voltage at the input 25 corresponding to a binary 1 permits Q1 and Q2 then Q3 to conduct with three stages of current gain, sinking current from the output 24, and clamping the output to a low level voltage corresponding to a binary 0. With Q2 conducting the Darlington transistor pullup element 21 is deprrived of base drive current and transistors Q5 and Q6 turn off. Diode D3 speeds up turn off of the transistor Q6. Current from high level voltage supply V.sub.cc is therefore no longer sourced to the output 24.
The speed at which pulldown element transistor Q3 discharges load capacitance at the output 24 during this transition from high to low at the output depends on the base current delivered at Q3. The process is enhanced by Diode D4 which diverts some of the output load discharge current to the collector of phase splitter stage Q2. The increased emitter current of transistor Q2 becomes the base current i.sub.b to pulldown transistor Q3 which current is then multiplied by the gain .beta. of transistor Q3 resulting in a larger collector current i.sub.c =.beta.i.sub.b, sinking current from the load and switching the output from binary 1 to binary 0 at a faster rate.
With a low level voltage corresponding to binary 0 at the input 25, diodes D1 and D2 conduct, depriving the two stage phase splitter transistor of base current so that they turn off. The diode D2 has been added to speed up the turn off of transistor Q2. With Q2 not conducting, voltage rises at the base of Q5 delivering base current so that Q5 becomes conducting, turning on Q6 and sourcing current from V.sub.cc to the output 24. At the same time pulldown transistor Q3 begins to turn off so that the output voltage can rise to high level binary 1.
The problem addressed by the present invention arises during this transition from low to high level voltage at the output in both of the transistor logic output devices illustrated in FIGS. 1 and 2. In the ideal situation during low to high transition at the output, the pulldown element transistor Q3 would turn off completely before a large current begins to flow from the pullup element Darlington transistor current source into the load capacitance. In the actual case, the pulldown element is turning off and the pullup element is turning on over a period of time with overlap so that some of the pullup current flows through the pulldown element to ground instead of into the load capacitance. One result is wasteful consumption of power.
The reason that pulldown element transistor Q3 does not turn off completely is because of the occurrence of parasitic capacitance in transistors, primarily the capacitance associated with the base-collector junction. Since pulldown transistor Q3 is required to conduct large amounts of current in sinking current from the load, it is physically larger than most of the transistors in the circuit and thus has a large base-collector capacitance. The equivalent circuit showing the effect of this base-collector junction capacitance on transistor Q3 is illustrated in FIG. 3 where the equivalent feedback capacitance accompanying the junction is shown as C.sub.bc connected across the base and collector of transistor Q3. This relatively large base to collector junction capacitance C.sub.bc in the pulldown element transistor is known as the "Miller capacitance". When the voltage or potential at the output is rising, a significant amount of current i.sub.bc is generated proportional to the rate of change of voltage across the base collector capacitance C.sub.bc. This current is also referred to as the "Miller current". Some of this Miller current flows into the base of Q3 designated in FIG. 3 as i.sub.b which base current is then multiplied by the gain .beta. of the transistor Q3 resulting in a large collector current i.sub.c =.beta.i.sub.b from Q3. This large current to ground diverts current from the pullup element reducing its effectiveness in charging up the load capacitance. As a result, there is wasteful power consumption and retardation or delay in the turnoff of pulldown element transistor Q3.
For further insight into the problem, reference is made to the squaring networks 16 and 26 of FIGS. 1 and 2 respectively coupled between the base of pulldown transistor Q3 and ground. The squaring network, consisting of transistor Q4 and resistors R7 and R8, is so named because its function is to square off the transfer characteristics of the device. When Q3 is conducting, a small current passes through resistor R7 saturating Q4. R8 must be large to limit the current flow away from the base of Q3 so that Q3 will not significantly be deprived of base current during the time when Q3 must conduct large current through its collector from the output. When Q2 and Q3 are turning off, R8 and Q4 pull current out of the base of Q3 to turn it off quickly.
The value of resistor R8 must therefore be a tradeoff. It must pass enough current to discharge Q3 rapidly during turnoff of the pulldown element. On the other hand, it must still be a large resistance, large enough to restrict current loss to ground so that current to the base of Q3 is not drained or sunk when Q3 is trying to conduct.
It is also frequently the case in conventional TTL and DTL transistor logic output devices that instead of a squaring network, a resistance alone is used coupled between the base of pulldown transistor Q3 and ground to facilitate turn off of Q3 during transition. Similarly, such resistance must be large and in that respect similar to R8 so the discussion here is also applicable.
The impact of this limitation of the squaring network 16 and 26 of FIGS. 1 and 2 and of the pulldown element base to ground turnoff resistance in some conventional transistor logic output devices is presented with reference to FIG. 3A. The objective during transition from low to high potential at the output is to turn off Q3 completely and quickly before the Darlingtion transistor current source pullup element begins to conduct. Because of the Miller capacitance and Miller current, and because of the high resistance limitations on the squaring network or pulldown transistor base turnoff resistance, this is not possible in the conventional circuits illustrated in FIGS. 1 and 2. The Miller capacitance C.sub.bc is always present at the base collector junction and cannot be eliminated. As shown in FIG. 3A for positive changing voltage during transition from low to high potential at the output current is generated and flows through C.sub.bc in the form of the Miller current i.sub.bc. This Miller current divides, one portion flowing through the squaring network resistance or through the base to ground resistance R8, this portion designated i.sub.r. The other portion flows into the base of pulldown transistor Q3 and is designated i.sub.b. This portion i.sub.b of the Miller current is multiplied by the gain .beta. of transistor Q3 so that Q3 will not turn off but continue to conduct current while the pullup element is trying to deliver current to the output. The result as described above is wasteful power consumption and delay in transition.
It is apparent that the current i.sub.b flowing into the base of Q3 must be eliminated to avoid the harmful effects of the Miller current. This base feedback current i.sub.b equals i.sub.bc -i.sub.r, that is the Miller current minus the portion diverted through resistance R8, and this could only be done if i.sub.r were equal to or greater than the Miller current i.sub.cb. However, this condition that i.sub.r be greater than or equal to the Miller current cannot be achieved in the conventional circuits of FIGS. 1 and 2 because resistance R8 must have such a large value for the reasons heretofore described. Q3 will therefore stay on until the voltage at the output stops changing from low to high as the Miller current across the Miller capacitance is proportional to the rate of change of potential across it. During this time, considerable current passes to ground from the pullup element through the still conducting pulldown transistor wasting power. This inefficient transition of the voltage output accompanying the parasitic capacitive feedback Miller current in prior art devices is shown graphically in FIGS. 3B and 3C alongside the more ideal characteristics sought and achieved by the present invention, the shaded portions representing some measure of the wasted power. These graphs are of course intended to present only a qualitative picture of a comparison of characteristics between the prior art transistor logic output devices and the devices of the present invention as exemplified and hereafter described with reference to FIGS. 4 and 5.